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INTEGRATED CIRCUITS
P3Z22V10 3V zero power, TotalCMOSTM, universal PLD device
Product specification Supersedes data of 1997 May 15 IC27 Data Handbook 1997 Jul 18
Philips Semiconductors
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
FEATURES
* Industry's first TotalCMOSTM 22V10 - both CMOS design and
process technologies
* Fast Zero Power (FZPTM) design technique provides ultra-low
power and high speed - Static current of less than 45A - Dynamic current 1/10 to 1/1000 that of competitive devices - Pin-to-pin delay of only 10ns
* Programmable output polarity * Synchronous preset/asynchronous reset capability * Security bit prevents unauthorized access * Electronic signature for identification * Design entry and verification using industry standard CAE tools * Reprogrammable using industry standard device programmers
DESCRIPTION
The P3Z22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Philips Semiconductors has used their FZPTM design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 5V operation, Philips Semiconductors offers the P5Z22V10 that offers high speed and low power in a 5V implementation. The P3Z22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.
* True Zero Power device with no turbo bits or power down
schemes
* Function/JEDEC map compatible with
Bipolar, UVCMOS, EECMOS 22V10s
* Multiple packaging options featuring PCB-friendly flow-through
pinouts (SOL and TSSOP) - 24-pin TSSOP--uses 93% less in-system space than a 28-pin PLCC - 24-pin SOL - 28-pin PLCC with standard JEDEC pin-out
* Available in commercial and industrial operating ranges * Supports mixed voltage systems-5V tolerant I/Os * Advanced 0.5 E2CMOS process * 1000 erase/program cycles guaranteed * 20 years data retention guaranteed * Varied product term distribution with up to 16 product terms per
output for complex functions
ORDERING INFORMATION
ORDER CODE P3Z22V10-DA P3Z22V10-DD P3Z22V10-DDH P3Z22V10-BA P3Z22V10-BD P3Z22V10-BDH P3Z22V10IBA P3Z22V10IBD P3Z22V10IBDH PACKAGE 28-pin PLCC 24-pin SOL 24-pin TSSOP 28-pin PLCC 24-pin SOL 24-pin TSSOP 28-pin PLCC 24-pin SOL 24-pin TSSOP PROPAGATION DELAY 10ns 10ns 10ns 15ns 15ns 15ns 15ns 15ns 15ns TEMPERATURE RANGE 0 to +70C 0 to +70C 0 to +70C 0 to +70C 0 to +70C 0 to +70C -40 to +85C -40 to +85C -40 to +85C OPERATING RANGE VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% VCC = 3.3V 10% DRAWING NUMBER SOT261-3 SOT137-1 SOT355-1 SOT261-3 SOT137-1 SOT355-1 SOT261-3 SOT137-1 SOT355-1
1997 Jul 18
2
853-2004 18193
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
PIN CONFIGURATIONS 28-Pin PLCC
IO/CLK VCC NC
PIN DESCRIPTIONS
PIN LABEL
F9 F8
DESCRIPTION Dedicated Input Not Connected Macrocell Input/Output Dedicated Input/Clock Input Supply Voltage Ground
I2
I1
I1 - I11 NC
25 F7 24 F6 23 F5 22 NC 21 F4 20 F3 19 F2
4 I3 I4 I5 NC I6 I7 I8 5 6 7 8 9 10 11 12 I9
3
2
1
28
27
26
F0 - F9 I0/CLK VCC GND
13 I10
14 GND
15 NC
16 I11
17 F0
18 F1
SP00474
24-Pin SOL and 24-Pin TSSOP
IO/CLK I1 I2 I3 I4 I5 I6 I7 I8 1 2 3 4 5 6 7 8 9 24 VCC 23 F9 22 F8 21 F7 20 F6 19 F5 18 F4 17 F3 16 F2 15 F1 14 F0 13 I11
I9 10 I10 11 GND 12
AP00475
1997 Jul 18
3
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
LOGIC DIAGRAM
CLK/I0 1 0 0 1 9 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43 AR
1 1 0 0 0 1 0 1
24
VCC
DAR SP
Q Q
23
F9
0 1
10
DAR Q Q 1 1 0 0 0 1 0 1
22
F8
20 I1 2 21
SP
0 1 1 1 0 0 0 1 0 1
DAR
33 I2 3 34
SP
Q Q
21
F7
0 1 1 1 0 0 0 1 0 1
DAR SP
Q Q
20
F6
48 I3 4 49
DAR SP Q Q 1 1 0 0 0 1 0 1 0 1
19
F5
65 I4 5 66
DAR SP Q Q
0 1 1 1 0 0 0 1 0 1
18
F4
82 I5 6 83
DAR SP Q Q
0 1 1 1 0 0 0 1 0 1
17
F3
97 I6 7 98
DAR Q Q
0 1 1 1 0 0 0 1 0 1
16
F2
110 I7 8 111
SP
0 1 1 1 0 0 0 1 0 1
DAR
121 I8 9 122 130
SP
Q Q
15
F1
0 1 1 1 0 0 0 1 0 1
DAR SP
Q Q
14
F0
I9
10 131 SP
0 1
I10 11 GND 12 0 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31 32 35 36 39 40 43
13
I11
NOTE: Programmable connection.
SP00059
1997 Jul 18
4
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
CLK/I0 1 11
I1 - I11
PROGRAMMABLE AND ARRAY (44 x 132)
8
10
12
14
16
16
14
12
10
8
RESET
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
OUTPUT MACRO CELL
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
SP00060A
Figure 1.
Functional Diagram 132 product terms: - 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) used to form logical sums - 10 output enable terms (one for each I/O) - 1 global synchronous preset product term - 1 global asynchronous clear product term At each input-line/product-term intersection there is an EEPROM memory cell which determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term which is connected to both the True and Complement of an input signal will always be FALSE, and thus will not affect the OR function that it drives. When all the connections on a product term are opened, a Don't Care state exists and that term will always be TRUE.
FUNCTIONAL DESCRIPTION
The P3Z22V10 implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. User-defined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility.
ARCHITECTURE OVERVIEW
The P3Z22V10 architecture is illustrated in Figure 1. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creation of logic functions. At the core of the device is a programmable electrically-erasable AND array which drives a fixed-OR array. With this structure, the P3Z22V10 can implement up to 10 sum-of-products logic expressions. Associated with each of the 10 OR functions is an I/O macrocell which can be independently programmed to one of 4 different configurations. The programmable macrocells allow each I/O to create sequential or combinatorial logic functions with either Active-High or Active-Low polarity.
Variable Product Term Distribution
The P3Z22V10 provides 120 product terms to drive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Logic Diagram). This distribution allows optimum use of device resources.
AND/OR Logic Array
The programmable AND array of the P3Z22V10 (shown in the Logic Diagram) is formed by input lines intersecting product terms. The input lines and product terms are used as follows: 44 input lines: - 24 input lines carry the True and Complement of the signals applied to the 12 input pins - 20 additional lines carry the True and Complement values of feedback or input signals from the 10 I/Os
1997 Jul 18
5
PRESET
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
S1
1 AR D CLK SP Q Q S1 S0 0 1 1 0 0 0 1 0 1 F 0 0 1 1
S0
0 1 0 1
OUTPUT CONFIGURATION
Registered/Active-LOW/Macrocell feedback Registered/Active-HIGH/Macrocell feedback Combinatorial/Active-LOW/Pin feedback Combinatorial/Active-HIGH/Pin feedback
0 = Unprogrammed fuse 1 = Programmed fuse
SP00484
Figure 2.
Output Macro Cell Logic Diagram
AR D CLK SP Q Q
S0 = 0 S1 = 0 F
S0 = 0 S1 = 1 F
a. Registered/Active-LOW
c. Combinatorial/Active-LOW
AR D CLK SP Q Q
S0 = 1 S1 = 0 F
S0 = 1 S1 = 1 F
b. Registered/Active-HIGH Figure 3.
d. Combinatorial/Active-HIGH Output Macro Cell Configurations
SP00376
Programmable I/O Macrocell
The output macrocell provides complete control over the architecture of each output. the ability to configure each output independently permits users to tailor the configuration of the P3Z22V10 to the precise requirements of their designs.
Output type
The signal from the OR array can be fed directly to the output pin (combinatorial function) or latched in the D-type flip-flop (registered function). The D-type flip-flop latches data on the rising edge of the clock and is controlled by the global preset and clear terms. When the synchronous preset term is satisfied, the Q output of the register will be set HIGH at the next rising edge of the clock input. Satisfying the asynchronous clear term will set Q LOW, regardless of the clock state. If both terms are satisfied simultaneously, the clear will override the preset.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 2, consists of a D-type flip-flop and two signal-select multiplexers. The configuration of each macrocell of the P3Z22V10 is determined by the two EEPROM bits controlling these multiplexers. These bits determine output polarity, and output type (registered or non-registered). Equivalent circuits for the macrocell configurations are illustrated in Figure 3.
1997 Jul 18
6
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
Program/Erase Cycles
The P3Z22V10 is 100% testable, erases/programs in seconds, and guarantees 1000 program/erase cycles.
from the I/O pin. In this case, the pin can be used as a dedicated input, a dedicated output, or a bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a reset condition and the Q output will be low. The actual output of the P3Z22V10 will depend on the programmed output polarity. The VCC rise must be monotonic.
Output Polarity
Each macrocell can be configured to implement Active-High or Active-Low logic. Programmable polarity eliminates the need for external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under the control of its associated programmable output enable product term. When the logical conditions programmed on the output enable term are satisfied, the output signal is propagated to the I/O pin. Otherwise, the output buffer is driven into the high-impedance state. Under the control of the output enable term, the I/O pin can function as a dedicated input, a dedicated output, or a bi-directional I/O. Opening every connection on the output enable term will permanently enable the output buffer and yield a dedicated output. Conversely, if every connection is intact, the enable term will always be logically FALSE and the I/O will function as a dedicated input.
Design Security
The P3Z22V10 provides a special EEPROM security bit that prevents unauthorized reading or copying of designs programmed into the device. The security bit is set by the PLD programmer, either at the conclusion of the programming cycle or as a separate step, after the device has been programmed. Once the security bit is set, it is impossible to verify (read) or program the P3Z22V10 until the entire device has first been erased with the bulk-erase function.
TotalCMOSTM Design Technique for Fast Zero Power
Philips is the first to offer a TotalCMOSTM SPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer SPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must accept low performance. Refer to Figure 4 and Table 1 showing the IDD vs. Frequency of our P3Z22V10 TotalCMOSTM SPLD.
Register Feedback Select
When the I/O macrocell is configured to implement a registered function (S1 = 0) (Figures 3a or 3b), the feedback signal to the AND array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial function (S1 = 1) (Figures 3c or 3d), the feedback signal is taken
30 TYPICAL 25
20
IDD (mA)
15
10
5
0
0 1
10
20
30
40
50
60
70
80
90
100
110
120
130
FREQUENCY (MHz)
SP00443
Figure 4.
Typical IDD vs. Frequency @ VDD = 3.3V, 25C (10-bit counter)
Table 1. Typical IDD vs. Frequency
VDD = 3.3V@25C FREQ (MHz) Typical IDD (mA) 1 0.2 10 1.5 20 3.0 30 4.5 40 6.0 50 7.4 60 8.9 70 10.4 80 11.8 90 13.2 100 14.5 110 15.8 120 17.0 130 18.2
1997 Jul 18
7
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
ABSOLUTE MAXIMUM RATINGS1
LIMITS SYMBOL VDD VI VOUT IIN IOUT TR TJ TSTG Supply voltage Input voltage Output voltage Input current Output current Allowable thermal rise ambient to junction Junction temperature range Storage temperature range PARAMETER MIN. -0.5 -0.5 -0.5 -30 -100 0 -40 -65 MAX. 4.6 5.52 5.52 30 100 75 150 150 V V V mA mA C C C UNIT
NOTES: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. 2. Except F7, where max = VDD + 0.5V.
OPERATING RANGE
PRODUCT GRADE Commercial Industrial TEMPERATURE 0 to +70C -40 to +85C VOLTAGE 3.3 10% V 3.3 10% V
1997 Jul 18
8
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0C Tamb +70C; 3.0 VDD 3.6V SYMBOL VIL VIH VI VOL VOH II IOZ IDDQ IDDD 1 ISC PARAMETER Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high In ut Input leakage current 3-Stated out ut leakage current output Standby current Dynamic current Short circuit output current TEST CONDITIONS VDD = 3.0V VDD = 3.6V VDD = 3.0V; IIN = -18mA VDD = 3.0V; IOL = 8mA VDD = 3.0V; IOH = -4mA VIN = 0 to VDD VIN = VDD to 5.5V2 VIN = 0 to VDD VIN = VDD to 5.5V2 VDD = 3.6V; Tamb = 0C VDD = 3.6V; Tamb = 0C @ 1MHz VDD = 3.6V; Tamb = 0C @ 50MHz 1 pin/time for no longer than 1 second Tamb = 25C; f = 1MHz Tamb = 25C; f = 1MHz Tamb = 25C; f = 1MHz MIN. 2 -1.2 0.5 2.4 -10 -10 -10 -10 25 .5 10 -15 10 10 10 10 45 2 15 -100 LIMITS TYP. MAX. 0.8 UNITS V V V V V A A A mA mA mA
CIN Input pin capacitance 8 pF CCLK Clock input capacitance 5 12 pF CI/O I/O pin capacitance 10 pF NOTES: 1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be affected. 2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0C Tamb +70C; 3.0 VDD 3.6V SYMBOL PARAMETER -B MIN. MAX. 15 MIN. -D MAX. 10 UNIT
tPD Input or feedback to non-registered output ns tSU Setup time from input, feedback or SP to Clock 4.5 3.5 ns tCO Clock to output 10 9 ns tCF Clock to feedback1 6 4.5 ns tH Hold time 0 0 ns tAR Asynchronous Reset to registered output 17 17 ns tARW Asynchronous Reset width 5 5 ns tARR Asynchronous Reset recovery time 6 6 ns tSPR Synchronous Preset recovery time 6 6 ns tWL Width of Clock LOW 3 3 ns tWH Width of Clock HIGH 3 3 ns tR Input rise time 20 20 ns tF Input fall time 20 20 ns fMAX1 Maximum internal frequency2 (1/tSU + tCF) 95 125 MHz fMAX2 Maximum external frequency1 (1/tSU + tCO) 69 80 MHz fMAX3 Maximum clock frequency1 (1/tWL + tWH) 167 167 MHz tEA Input to Output Enable 9 9 ns tER Input to Output Disable 9 9 ns Capacitance CIN Input pin capacitance 10 10 pF COUT Output capacitance 10 10 pF NOTES: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 1997 Jul 18 9
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: -40C Tamb +85C; 3.0 VDD 3.6V SYMBOL VIL VIH VI VOL VOH II IOZ IDDQ IDDD 1 PARAMETER Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current In ut 3-Stated out ut leakage current output Standby current Dynamic current TEST CONDITIONS VDD = 3.0V VDD = 3.6V VDD = 3.0V; IIN = -18mA VDD = 3.0V; IOL = 8mA VDD = 3.0V; IOH = -4mA VIN = 0 to VDD VIN = VDD to 5.5V2 VIN = 0 to VDD VIN = VDD to 5.5V2 VDD = 3.6V; Tamb = -40C VDD = 3.6V; Tamb = -40C @ 1MHz VDD = 3.6V; Tamb = -40C @ 50MHz 1 pin/time for no longer than 1 second Tamb = 25C; f = 1MHz Tamb = 25C; f = 1MHz Tamb = 25C; f = 1MHz MIN. 2 -1.2 0.5 2.4 -10 -10 -10 -10 30 .5 10 -15 10 10 10 10 45 3 20 -100 LIMITS TYP. MAX. 0.8 UNITS V V V V V A A A A A mA mA mA
ISC
Short circuit output current
CIN Input pin capacitance 8 pF CCLK Clock input capacitance 5 12 pF CI/O I/O pin capacitance 10 pF NOTES: 1. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where current may be affected. 2. Does not apply to F7.
AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES
Industrial: -40C Tamb +85C; 3.0 VDD 3.6V SYMBOL PARAMETER LIMITS MIN. MAX. 15 UNIT
tPD Input or feedback to non-registered output ns tSU Setup time from input, feedback or SP to Clock 5 ns tCO Clock to output 10.5 ns tCF Clock to feedback1 6 ns tH Hold time 0 ns tAR Asynchronous Reset to registered output 17 ns tARW Asynchronous Reset width 5 ns tARR Asynchronous Reset recovery time 6 ns tSPR Synchronous Preset recovery time 6 ns tWL Width of Clock LOW 3 ns tWH Width of Clock HIGH 3 ns tR Input rise time 20 ns tF Input fall time 20 ns fMAX1 Maximum internal frequency2 (1/tSU + tCF) 91 MHz fMAX2 Maximum external frequency1 (1/tSU + tCO) 65 MHz fMAX3 Maximum clock frequency1 (1/tWL + tWH) 167 MHz tEA Input to Output Enable 11 ns tER Input to Output Disable 11 ns Capacitance CIN Input pin capacitance 10 pF COUT Output capacitance 12 pF NOTES: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 2. These parameters measured with a 10-bit up counter, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 10
1997 Jul 18
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
TEST LOAD CIRCUIT
VCC +3.3V S1
C1
C2 I0 F0
R1
R2 DUT INPUTS In CK Fn OE GND
CL
NOTE: C1 and C2 are to bypass VCC to GND. R1 = 300, R2 = 300, CL = 35pF.
SP00478
THEVENIN EQUIVALENT
VL = 1.65V
150
DUT OUTPUT
35pF
SP00479A
VOLTAGE WAVEFORM
+3.0V 90%
10% 0V tR 1.5ns tF 1.5ns
MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
Input Pulses
SP00368
1997 Jul 18
11
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
SWITCHING WAVEFORMS
INPUT OR FEEDBACK VT tPD COMBINATORIAL OUTPUT VT CLOCK INPUT OR FEEDBACK VT tS tH VT tCO REGISTERED OUTPUT VT
Combinatorial Output
Registered Output
INPUT tWH tER CLOCK VT OUTPUT tWL
VT tEA VOH - 0.5V VOL + 0.5V VT
Clock Width
Input to Output Disable/Enable
tARW INPUT ASSERTING ASYNCHRONOUS RESET VT tAR REGISTERED OUTPUT VT tARR CLOCK VT REGISTERED OUTPUT CLOCK INPUT ASSERTING SYNCHRONOUS PRESET VT tS tH VT tCO VT tSPR VT
Asynchronous Reset NOTES: 1. VT = 1.5V. 2. Input pulse amplitude 0V to 3.0V. 3. Input rise and fall times 2.0ns max.
Synchronous Preset
SP00065
"AND" ARRAY - (I, B)
I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B I, B
P, D STATE INACTIVE1 CODE O STATE TRUE
P, D CODE H STATE COMPLEMENT
P, D CODE L STATE DON'T CARE
P, D CODE --
SP00008
NOTE: 1. This is the initial state. 1997 Jul 18 12
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
PLCC28: plastic leaded chip carrer; 28 leads; pedestal
P3Z22V10
SOT261-3
1997 Jul 18
13
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
SO24: plastic small outline package; 24 leads; body width 7.5 mm
P3Z22V10
SOT137-1
1997 Jul 18
14
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
P3Z22V10
SOT355-1
1997 Jul 18
15
Philips Semiconductors
Product specification
3V zero power, TotalCMOSTM, universal PLD device
P3Z22V10
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A.
Philips Semiconductors
1997 Jul 18 16

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